Some pros and cons of HLS
I’ve started working on a HLS project. Initially, I have heard a lot of good things about HLS, but now I’ve also started to realize some of its problems. This is an unfinished post, and it’s based on my personal experience as someone who is not an expert on FPGA programming.
- Provide a really good environment for co-development between firmware and software (including test bench).
- Provide the firmware emulation with bitwise accurate results. The emulation can be used outside of Vivado for a lot of studies.
- Allow non-FPGA engineers to collaborate on the algorithm development. This helps physicists to take over some work load, which is useful for projects where the num of physicsts >> num of engineers.
- Facilitate interfacing with C++ and Python. Xilinx has started providing first-class HLS libraries (e.g. Vitis Libraries) to interact with its FPGAs. This helps lowering the barrier to adopt FPGAs.
- The output Verilog code generated by the Vivado HLS tool is not human readable.
- Due to the above, it’s very hard to figure out how to optimize the algorithm. Maybe an experienced FPGA engineer could do that, but it’s really difficult for me. I have no idea how should I structure a particular for loop, or which pragma directive should I use, or whether a function should be inlined, etc in order to achieve the results that I want, since I couldn’t understand the translation process.
- The Vivado HLS tool is way too slow. It takes several hours (sometimes >3 hours) to compile my codes after a single change.
- A lot of configurations need to be passed as compile-time arguments (e.g. loop bounds), rendering the C++ codes also kind of unreadable. In C++11 (the standard supported by the Vivado HLS tool), the use of
constexpris very restrictive.